The present disclosure relates to a semiconductor device having through vias.
In recent years, a stacked semiconductor device in which a plurality of semiconductor chips are stacked has been developed to provide the semiconductor device with higher functionality and higher integration. However, in most stacked semiconductor devices, semiconductor chips that have been stacked using wire bonding are electrically connected to each other via an interconnect substrate such as an interposer. Accordingly, the size of a stacked semiconductor device corresponds to a size obtained by adding the size of a space for wire routing to the sizes of the semiconductor chips, which limits the miniaturization of the stacked semiconductor device. In such a stacked semiconductor device, the use of wire bonding increases a wiring length, which increases wiring resistance and also limits a high-speed operation.
As a solution to the foregoing problem, a stacked semiconductor device (see Japanese Laid-Open Patent Publication No. 10-163411) as shown in FIG. 10 has been proposed. In the device, a plurality of stacked semiconductor chips are electrically connected using through vias formed by forming through holes in the semiconductor chips, and filling the through holes with a conductive resin or metal. Specifically, as shown in FIG. 10, the stacked semiconductor device in which semiconductor chips 1001D, 1001C, 1001B, and 1001A are successively stacked in an ascending order is provided with a plurality of through vias 1003. The individual semiconductor chips are bonded to each other using an insulating resin 1004. Around the respective through vias 1003 at the back surface of each of the semiconductor chips, via extraction pads 1002 are provided individually. Note that, to achieve stable electrical connections at the via extraction pads 1002, voids 1005 are formed around the respective through vias 1003 in the insulating resin 1004, and are each filled with the same material as that of the through vias 1003.
In the structure shown in FIG. 10, the stacked semiconductor chips can be directly connected to each other so that the size of the entire stacked semiconductor device is determined only by the sizes of the semiconductor chips. Also, in the structure shown in FIG. 10, the semiconductor chips can be electrically connected to each other with a wiring length shorter than in the case where the semiconductor chips are electrically connected to each other by wire bonding. This allows a reduction in wiring resistance, and enables a high-speed operation. Furthermore, since it is possible to reduce the height of the stacked semiconductor device by thinning each of the semiconductor chips to be stacked, the size of the entire stacked semiconductor device can be reduced as compared to that of a conventional structure.
As an example of a typical layout of the through vias described above, there is a layout of the through vias in a stacked semiconductor device (see Japanese Laid-Open Patent Publication No. 2004-335948) as shown in FIG. 11. In a device 1100, through vias 1105 are arranged with an equal pitch over the entire device.